Photolithography is a process commonly used in semiconductor fabrication for selectively removing portions of a thin film from or depositing portions of a film onto discrete areas of a surface of a semiconductor wafer. A typical photolithography process includes spin coating a layer of a radiation-sensitive material (commonly referred to as a “photoresist”) onto the surface of the semiconductor wafer. The semiconductor wafer is then exposed to a pattern of radiation that chemically modifies a portion of the photoresist incident to the radiation. The process further includes removing either the exposed portion or the unexposed portion of the photoresist from the surface of the semiconductor wafer with a chemical solution (e.g., a “developer”) to form a pattern of openings through the photoresist corresponding to the pattern of radiation. Subsequently, portions of the thin film on the surface of the semiconductor wafer can be selectively removed, or portions of a thin film can be deposited onto the surface of the wafer, through the openings of the photoresist mask. The photolithography process can be repeated to form layers of microelectronic features on or in the wafer. Vias, such as through-silicon vias (TSVs), are one type of structure that can electrically connect components in different layers.
An important aspect of semiconductor processing is aligning the wafer with respect to a processing tool, and in particular photolithography tools. Modern integrated circuits have multiple layers (e.g., 30 or more) that need to be aligned as they are formed on the wafer. Traditionally, one or more alignment marks are formed on the wafer at the beginning of a manufacturing process. The alignment marks provide an indicator of a reference point or reference structure of a wafer. The marks are used to determine the relative orientation of the wafer with respect to a processing tool. However, typical fabrication and packaging processes, such as oxide growth, planarization, or metal deposition, often change critical features of the marks. For example, deposition processes, oxide growth, and removal processes can change marks that start out as trenches to mesas, or the processes can alter the color, contrast, or other properties of the marks. The changes in the alignment marks may cause misalignment among the layers, which in turn can cause short-circuiting, misaligned vias, disconnections, and other forms of device failure.
In addition to or in lieu of dedicated alignment marks, TSVs or other types of vias formed on the wafer can be used to align the wafer with a processing tool. For example, a set of TSVs or other components of a wafer can be used as an alignment mark in a manner similar to dedicated alignment marks. In the case of TSVs, the size, shape, location, and topography of individual TSVs can vary and be within manufacturing tolerances. However, such variances in the TSVs can make it difficult to use sets of TSVs as alignment marks.
One alignment method is manual alignment. Operators using a microscope view the position of a wafer and make adjustments as needed by using a computer that controls an actuator to move a wafer support carrying the wafer. This method is slow, is inaccurate, and has a high yield loss due to misalignment even among the most conscientious operators. Other methods such as wafer probing and mechanically scanning point sensors have automated the manual process. However, these methods continue to produce wafers with high yield loss or devices that malfunction due to misalignment. Accordingly, the need exists for systems and methods that reduce misalignment.